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10-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer ADV7401
FEATURES
Four 10-bit ADCs sampling up to 140 MHz (140 MHz speed grade only) 12 analog input channel mux SCART fast blank support Internal antialias filters NTSC/PAL/SECAM color standards support 525p-/625p-component progressive scan support 720p-/1080i-component HDTV support Digitizes RGB graphics up to 1280 x 1024 @ 75 Hz (SXGA) (140 MHz speed grade only) 24-bit digital input port supports data from DVI/HDMI Rx IC Any-to-any, 3 x 3 color-space conversion matrix Industrial temperature range (-40C to +85C) 12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface Programmable interrupt request output pin VBI data slicer (including teletext)
GENERAL DESCRIPTION
The ADV7401 is a high quality, single chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-video into a digital ITU-R BT.656 format. The ADV7401 also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many other HD and SMPTE standards. Graphic digitization is also supported by the ADV7401; it is capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ADV7401's ability to simultaneously process CVBS and standard definition RGB signals. The mixing of these signals is controlled by the fast blank pin. The ADV7401 contains two main processing sections. The first is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types. The second is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. For more specific descriptions of the ADV7401 features, see the Detailed Functionality and Detailed Description sections.
APPLICATIONS
LCD/DLPTM rear projection HDTVs PDP HDTVs CRT HDTVs LCD/DLP front projectors LCD TV (HDTV ready) HDTV STBs with PVR Hard-disk-based video recorders Multiformat scan converters DVD recorders with progressive scan input support AVR receiver
Rev. SpA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
ADV7401 TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3 Electrical Characteristics ................................................................. 4 Video Specifications ......................................................................... 6 Timing Characteristics..................................................................... 7 Analog Specifications....................................................................... 8 Absolute Maximum Ratings............................................................ 9 Stress Ratings ................................................................................ 9 Package Thermal Performance................................................... 9 Thermal Specifications ................................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Timing Diagrams............................................................................ 12 Detailed Functionality ................................................................... 13 Analog Front End ....................................................................... 13 SDP Pixel Data Output Modes ................................................. 13 CP Pixel Data Output Modes ................................................... 13 Composite and S-Video Processing......................................... 13 Component Video Processing .................................................. 14 RGB Graphics Processing ......................................................... 14 Digital Video Input Port............................................................ 14 General Features......................................................................... 14 Detailed Description ...................................................................... 15 Analog Front End....................................................................... 15 Standard Definition Processor (SDP)...................................... 15 Component Processor ............................................................... 15 Pixel Input/Output Formatting .................................................... 17 Recommended External Loop Filter Components.................... 18 Typical Connection Diagram ....................................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
9/05--Rev. Sp 0 to Rev. SpA Deleted EDTV.....................................................................Universal Added AVR Receiver to Applications Section.............................. 1 Changes to Table 3............................................................................ 7 Changes to Figure 2........................................................................ 10 Changes to Function Descriptions of Pin 37 and Pin 38 .......... 11 Change Pin 70 Type........................................................................ 11 Change to Crystal MHz Unit Value ............................................. 13 Added Pixel Input Information to Table 9 and Table 10 ........... 17 4/05--Revision Sp0: Initial Version
Rev. SpA | Page 2 of 20
ADV7401
MACROVISION DETECTION VBI DATA RECOVERY 10 A/D 10 Y LUMA FILTER LUMA RESAMPLE LUMA 2D COMB (5H MAX) CVBS/Y DATA PREPROCESSOR ANTIALIAS FILTER 10 A/D 10 DECIMATION AND DOWNSAMPLING 10 FILTERS 10 10 A/D CVBS C Cr Cb Y Cr Cb CHROMA DEMOD CHROMA FILTER CHROMA RESAMPLE Cr CHROMA 2D COMB (4H MAX) Cb FSC RECOVERY SYNC EXTRACT RESAMPLE CONTROL STANDARD AUTODETECTION
STANDARD DEFINITION PROCESSOR
FUNCTIONAL BLOCK DIAGRAM
CLAMP
AIN1 12 TO AIN12 ANTIALIAS FILTER 10 A/D
INPUT MUX
CLAMP
8 16 8 8 P29-P22 P19-P12 P9-P2 PIXEL DATA
CVBS S-VIDEO YPrPb SCART- (RGB + CVBS) GRAPHICS RGB ANTIALIAS FILTER ANTIALIAS FILTER
CLAMP
CLAMP
HS VS FIELD/DE
OUTPUT FIFO AND FORMATTER
Figure. 1.
FB
FAST BLANK OVERLAY CONTROL AND AV CODE INSERTION
Rev. SpA | Page 3 of 20
STDI ACTIVE PEAK AND AGC 8 8 8 COLORSPACE CONVERSION 10 10 10 DIGITAL FINE CLAMP GAIN CONTROL MACROVISION DETECTION
SCLK SCLK2 SDA SDA2 ALSB
SERIAL INTERFACE CONTROL AND VBI DATA
LLC1
DCLK_IN
SYNC PROCESSING AND CLOCK GENERATION
SFL/ SYNCOUT
DE_IN HS_IN VS_IN
SSPD
COMPONENT PROCESSOR CGMS DATA EXTRACTION
SOG SOY
INT
XTAL XTAL1 OFFSET CONTROL AV CODE INSERTION 24
DIGITAL INPUT PORT
P40-P31 P29-P20 24 P11-P10 P1-P0
DVI or HDMI
05340-001
ADV7401
ADV7401
ELECTRICAL CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. Operating temperature range, unless otherwise noted. Table 1.
Parameter 1, 2 , 3 STATIC PERFORMANCE 4 , 5 Resolution (each ADC) Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Differential Nonlinearity Differential Nonlinearity Differential Nonlinearity Differential Nonlinearity DIGITAL INPUTS 8 Input High Voltage 9 Input Low Voltage 10 Input High Voltage Input Low Voltage Input Current Input Capacitance8 DIGITAL OUTPUTS Output High Voltage 12 Output Low Voltage12 High Impedance Leakage Current Output Capacitance8 POWER REQUIREMENTS8 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Core Supply Current Symbol N INL INL INL INL INL DNL DNL DNL DNL DNL VIH VIL VIH VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD 1.65 3.0 1.71 3.15 CVBS input sampling at 54 MHz Graphics RGB sampling at 135 MHz SCART RGB FB sampling at 54 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 135 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 135 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 135 MHz SCART RGB FB sampling at 54 MHz Sync bypass function 1.8 3.3 1.8 3.3 105 137 106 4 19 11 12 99 242 269 2.25 16 20 ISOURCE = 0.4 mA ISINK = 3.2 mA Pins listed in Note 13 All other output pins 2.4 0.4 60 10 20 2 3.6 1.89 3.45 Test Conditions Min Typ Max 10 2.5 Unit Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB V V V V
A A
BSL at 27 MHz (at a 10-bit level) BSL at 54 MHz (at a 10-bit level) BSL at 74 MHz (at a 10-bit level) BSL at 110 MHz (at an 8-bit level) 6 BSL at 135 MHz (at an 8-bit level) 7 At 27 MHz (at a 10-bit level) At 54 MHz (at a 10-bit level) At 74 MHz (at a 10-bit level) At 110 MHz (at an 8-bit level)6 At 135 MHz (at an 8-bit level)7 2
0.6 -0.6/+0.7 1.4 0.9 1.5 -0.2/+0.25 -0.2/+0.25 0.9 -0.2/+1.5 -0.9/+3.0
-0.99/+2.5
0.8 HS_IN, VS_IN low trigger mode HS_IN, VS_IN low trigger mode Pins listed in Note 11 All other input pins 0.7 -60 -10 0.3 +60 +10 10
pF V V
A A
pF V V V V mA mA mA mA mA mA mA mA mA mA mA mA ms
Digital I/O Supply Current PLL Supply Current Analog Supply Current 14
IDVDDIO IPVDD IAVDD
Power-Down Current Green Mode Power-Down Power-Up Time
1
IPWRDN IPWRDNG TPWRUP
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C (0C to 70C temperature range for ADV7401KSTZ-140). 3 All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00. 4 All ADC linearity tests performed at input range of full scale - 12.5%, and at zero scale + 12.5%.
2
Rev. SpA | Page 4 of 20
ADV7401
5 6
Max INL and DNL specifications obtained with part configured for component video input. Specification for ADV7401BSTZ-110 and ADV7401KSTZ-140 only. 7 Specification for ADV7401KSTZ-140 only. 8 Guaranteed by characterization. 9 To obtain specified VIH level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, then VIH on Pin 38 = 1.2 V. 10 To obtain specified VIL level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, then VIL on Pin 38 = 0.4 V. 11 Pins 1, 2, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 79, 83, 84, 87, 88, 95, 96, 97, 100. 12 VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4. 13 Pins 3, 13, 14, 19, 24, 29, 30, 31, 32, 33, 34, 45. 14 Analog current measurements for CVBS made with ADC0 powered up only, For RGB, ADC0, ADC1 and ADC2 powered up only, for SCART FB, all ADCs powered up.
Rev. SpA | Page 5 of 20
ADV7401 VIDEO SPECIFICATIONS
@ AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted. Table 2.
Parameter 1, 2 , 3 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted SNR Unweighted Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock in Time Sync Depth Range 4 Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy
1 2
Symbol DP DG LNL
Test Conditions CVBS input, modulated 5 step CVBS input, modulated 5 step CVBS input, 5 step Luma ramp Luma flat field
Min
Typ 0.5 0.5 0.5
Max
Unit degree % % dB dB dB
54 58
56 60 60 +5 70 1.3 60
-5 40
20 5 2 100 HUE CL_AC 5 0.5 0.4 0.2 CVBS, 1 V input CVBS, 1 V input 1 1 1 1
200 200
% Hz kHz line % % field line degree % % % degree % % %
400
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C (0C to 70C temperature range for ADV7401KSTZ-140). 3 Guaranteed by characterization. 4 Nominal sync depth is 300 mV at 100% sync depth range.
Rev. SpA | Page 6 of 20
ADV7401 TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted. Table 3.
Parameter 1, 2 , 3 SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC1 Frequency Range 4 I2C PORT 5 SCLK Frequency SCLK Min Pulse Width High SCLK Min Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio DATA and CONTROL OUTPUTS Data Output Transition Time SDR (SDP) 6 Data Output Transition Time SDR (SDP)6 Data Output Transition Time SDR (CP) 7 Data Output Transition Time SDR (CP)7 Data Output Transition Time DDR (CP)7, 8 Data Output Transition Time DDR (CP)7, 8 Data Output Transition Time DDR (CP)7, 8 Data Output Transition Time DDR (CP)7, 8 DATA and CONTROL INPUTS5 Input Setup Time (Digital Input Port) Input Hold Time (Digital Input Port)
1 2
Symbol
Test Conditions
Min
Typ 28.63636
Max
Unit MHz ppm kHz MHz kHz s s s s ns ns ns s ms
14.8 12.825
50 110 140 400
t1 t2 t3 t4 t5 t6 t7 t8
0.6 1.3 0.6 0.6 100 300 300 0.6 5
t9:t10 t11 t12 t13 t14 t15 t16 t17 t18 Negative clock edge to start of valid data End of valid data to negative clock edge End of valid data to negative clock edge Negative clock edge to start of valid data Positive clock edge to end of valid data Positive clock edge to start of valid data Negative clock edge to end of valid data Negative clock edge to start of valid data HS_IN, VS_IN DE_IN, data inputs HS_IN, VS_IN DE_IN, data inputs
45:55
55:45 3.6 2.4 2.8 0.1
% duty cycle ns ns ns ns ns ns ns ns
-4 + TLLC1/4 0.25 + TLLC1/4 -2.95 + TLLC1/4 -0.5 + TLLC1/4
t19 t20
9 2.2 7 2
ns ns ns ns
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C (0C to 70C temperature range for ADV7401KSTZ-140). 3 Guaranteed by characterization. 4 Maximum LLC1 frequency is 80 MHz for ADV7401BSTZ-80 and is 110 MHz for ADV7401BSTZ-110. 5 TTL input values are 0 V to 3 V, with rise/fall times 3 ns, measured between the 10% and 90% points. 6 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4. 7 CP timing figures obtained using max drive strength value (0xFF) in register subaddress 0xF4. 8 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
Rev. SpA | Page 7 of 20
ADV7401 ANALOG SPECIFICATIONS
@ AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p. Table 4.
Parameter 1, 2 , 3 CLAMP CIRCUITRY External Clamp Capacitor Input Impedance 4 Input Impedance of Pin 51 (FB) CML ADC Full-Scale Level ADC Zero-Scale level ADC Dynamic Range Clamp Level (When Locked) Test Conditions Min Typ 0.1 10 20 1.86 CML + 0.8 V CML - 0.8 V 1.6 CML - 0.292 V CML - 0.4 V CML - 0.292 V CML - 0 V CML - 0.3 V CML - 0.3 V 0.75 0.9 17 17 Max Unit F M k V V V V V V V V V V mA mA A A
Clamps switched off
Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current
1 2 3
CVBS input SCART RGB input (R, G, B signals) S-Video input (Y signal) S-Video input (C signal) Component input (Y, Pr, Pb signals) PC RGB input (R, G, B signals) SDP only SDP only SDP only SDP only
The min/max specifications are guaranteed over this range. Temperature range TMIN to TMAX: -40C to +85C (0C to 70C temperature range for ADV7401KSTZ-140). Guaranteed by characterization. 4 Except Pin 51 (FB).
Rev. SpA | Page 8 of 20
ADV7401 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO to PVDD DVDDIO to DVDD AVDD to PVDD AVDD to DVDD Digital Inputs Voltage to DGND Digital Outputs Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 2.2 V 2.2 V 4V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V DGND - 0.3 V to DVDDIO + 0.3 V DGND - 0.3 V to DVDDIO + 0.3 V AGND - 0.3 V to AVDD + 0.3 V 125C -65C to +150C 260C
STRESS RATINGS
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part the user is advised to turn off any unused ADCs . The junction temperature must always stay below the maximum junction temperature (TJ MAX) of 125C. This equation shows how to calculate the junction temperature: TJ = TA Max + (JA x WMax) where: TA Max = 85C. JA = 30C/W. WMax = ((AVDD x IAVDD) + (DVDD x IDVDD) + (DVDDIO x IDVDDIO) + (PVDD x IPVDD)).
THERMAL SPECIFICATIONS
Table 6.
Thermal Characteristics Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance Symbol JC JA Test Conditions 4-layer PCB with solid ground plane 4-layer PCB with solid ground plane (still air) Typ 7 30 Unit C/W C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. SpA | Page 9 of 20
ADV7401 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HS_IN/CS_IN FIELD/DE RESET
78
SCLK1
DGND
DVDD
VS_IN
SDA1
ALSB
DE_IN
P33
P34
P35
P36
P16
P17
100
99
95
P18
VS
P19
89
88
P37
87
P38
84
P39
P40
77
93
92
82
97
96
91
90
86
85
81
80
98
94
P32 P31 INT CS/HS DGND DVDDIO P15 P14 P13 P12 DGND DVDD P29 P28 SFL/SYNC_OUT SCLK2 DGND DVDDIO SDA2 P11 P10 P9 P8 P27 P7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN 1
83
79
76
AIN6
75 74 73 72 71 70 69 68 67
SOY
AIN12 AIN5 AIN11 AIN4 AIN10 TEST0 CAPC2 CAPC1 BIAS AGND CML REFOUT AVDD CAPY2 CAPY1 AGND TEST1 AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 SOG FB
ADV7401
66 65 64
LQFP TOP VIEW (Not to Scale)
63 62 61 60 59 58 57 56 55 54 53 52 51
27
31
37
38
39
42
48
49
26
33
34
44
29
30
35
36
40
41
45
46
28
32
43
47
50
ELPF
DCLK_IN
XTAL1
DGND
DVDD
PVDD
PVDD
XTAL
AGND
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 5, 11, 17, 40, 89 49, 50, 60, 66 6, 18 12, 39, 90 63 47, 48 51 54, 56, 58, 72, 74, 76, 53, 55, 57, 71, 73, 75 42, 41, 28, 27, 26, 25, 23, 22, 10, 9, 8, 7, 94, 93, 92, 91 33, 32, 31, 30, 29, 24, 14, 13 44, 43, 21, 20, 45, 34, 2, 1, 100, 97, 96, 95, 88, 87, 84, 83 3 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD FB AIN1 to AIN12 P2 to P9, P12 to P19 P22 to P29 P0 to P1, P10 to P11, P20 to P21, P31 to P40 INT Type G G P P P P I I O I/O I O Function Digital Ground. Analog Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (3.3 V). PLL Supply Voltage (1.8 V). Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals. Analog Video Input Channels. Video Pixel Output Port. Video Input/Output Port Video Pixel Input Port. Interrupt. This pin can be active low or active high. When SDP/CP status bits change this pin triggers. The set of events that triggers an interrupt is under user control.
Rev. SpA | Page 10 of 20
AGND
LLC1
05340-002
P6
P25
P4
P3
P1
P26
P23
P22
P21
P0
P24
P20
P5
P2
ADV7401
Pin No. 4 Mnemonic HS/CS Type O Function HS is a Horizontal Synchronization Output Signal (SDP and CP modes). CS is a Digital Composite Synchronization Signal (and can be selected while in CP mode). Vertical Synchronization Output Signal (SDP and CP modes). Field Synchronization Output Signal (all interlaced video modes). This pin also can be enabled as a Data Enable signal (DE) in CP mode to allow direct connection to a HDMI/DVI Tx IC. I2C Port Serial Data Input/Output Pins. SDA1 is the data line for the control port and SDA2 is the data line for the VBI readback port. I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock line for the control port and SCLK2 is the clock line for the VBI data readback port. This pin selects the I2C address for the ADV7401 control and VBI readback ports. ALSB set to Logic 0 sets the address for a write to control port of 0x40 and the readback address for the VBI port of 0x21. ALSB set to a logic high sets the address for a write to control port of 0x42 and the readback address for the VBI port of 0x23. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7401 circuitry. LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz to 140 MHz for ADV7401KSTZ-140; 12.825 MHz to 110 MHz for ADV7401BSTZ-110; 12.825 MHz to 80 MHz for ADV7401BSTZ-80). Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the ADV7401. This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7401. In crystal mode, the crystal must be a fundamental crystal. The recommend external loop filter must be connected to this ELPF pin. This pin should be left unconnected or alternatively tied to AGND. This pin should be left unconnected. Subcarrier Frequency Lock (SFL). This pin contains a serial output stream which can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. SYNC_OUT is the sliced sync output signal available only in CP mode. Internal Voltage Reference Output. Common-Mode Level Pin (CML) for the internal ADCs. ADC Capacitor Network. ADC Capacitor Network. External Bias Setting Pin. Connect the recommended resistor (1.35 k) between pin and ground. Can be configured in CP mode to be either a digital HS input signal or a digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode. VS Input Signal. Used in CP mode for 5-wire timing mode. Data Enable Input Signal. Used in 24-bit digital input port mode (for example, processing 24-bit RGB data from a DVI Rx IC). Clock Input Signal. Used in 24-bit digital input mode (for example, processing 24-bit RGB data from a DVI Rx IC) and also in digital CVBS input mode. Sync on Green Input. Used in embedded sync mode. Sync on Luma Input. Used in embedded sync mode.
99 98
VS FIELD/DE
O O
81, 19 82, 16
SDA1, SDA2 SCLK1, SCLK2
I/O I
80
ALSB
I
78 36
RESET LLC1
I O
38 37
XTAL XTAL1
I O
46 70 59 15
ELPF TEST0 TEST1 SFL/SYNC_OUT
O NC O O
64 65 61, 62 68, 69 67 86
REFOUT CML CAPY1, CAPY2 CAPC1, CAPC2 BIAS HS_IN/CS_IN
O O I I O I
85 79 35
VS_IN DE_IN DCLK_IN
I I I
52 77
SOG SOY
I I
Rev. SpA | Page 11 of 20
ADV7401 TIMING DIAGRAMS
t3
SDA1/SDA2
t5
t3
t6
SCLK1/SCLK2
t1
05340-003
05340-008
t2
t7
t4
t8
Figure 3. I2C Timing
t9
LLC1
t10
t11
05340-004
P2-P9, P12-P19, P22-P29, VS, HS, FIELD/DE, SFL/SYNC_OUT
t12
Figure 4. Pixel Port and Control SDR Output Timing (SD Core)
t9
LLC1
t10
t13 t14
P2-P9, P12-P19, P22-P29
05340-005
Figure 5. Pixel Port and Control SDR Output Timing (CP Core)
LLC1
t16 t15
P6-P9, P12-P19
t18
05340-006
t17
Figure 6. Pixel Port and Control DDR Output Timing (CP Core)
DCLK_IN
t9
CONTROL INPUTS HS_IN VS_IN DE_IN
t10
t20
P0-P1, P10-P11, P20-P21, P22-P29, P31-P32, P33-P40
t19
Figure 7. Digital Input Port and Control Input Timing
Rev. SpA | Page 12 of 20
ADV7401 DETAILED FUNCTIONALITY
ANALOG FRONT END
* * * * * Four high quality 10-bit ADCs enable true 8-bit video decoder 12 analog input channel mux enables multisource connection without the requirement of an external mux Four current and voltage clamp control loops ensure any dc offsets are removed from the video signal SCART functionality and SD RGB overlay on CVBS controlled by fast blank input Four internal antialias filters to remove out-of-band noise on standard definition input video signals * * * * * * Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners IF filter block compensates for high frequency luma attenuation due to tuner SAW filter Chroma transient improvement (CTI) Luminance digital noise reduction (DNR) Color controls include hue, brightness, saturation, contrast, and Cr and Cb offset controls Certified Macrovision copy protection detection on composite and S-video for all worldwide formats (PAL/NTSC/SECAM) 4x oversampling (54 MHz) for CVBS, S-video, and YUV modes Line-locked clock output (LLC) Letterbox detection supported Free-run output mode provides stable timing when no video input is present Vertical blanking interval data processor TeleText Video Programming System (VPS) Vertical Interval Time Codes (VITC) Closed captioning (CC) and extended data service (EDS) Wide screen signaling (WSS) Copy generation management system (CGMS) GemstarTM 1x/2x electronic program guide compatible * * * * Clocked from a single 28.63636 MHz crystal Subcarrier frequency lock (SFL) output for downstream video encoder Differential gain typically 0.5% Differential phase typically 0.5
SDP PIXEL DATA OUTPUT MODES
* * * 8-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD 16-bit YCrCb with embedded time codes and/or HS, VS, and FIELD 24-bit YCrCb with embedded time codes and/or HS, VS, and FIELD
* * * * *
CP PIXEL DATA OUTPUT MODES
* * * * * Single data rate (SDR) 8-bit 4:2:2 YCrCb for 525i, 625i Single data rate (SDR) 16-bit 4:2:2 YCrCb for all standards Single data rate (SDR) 24-bit 4:4:4 YCrCb/RGB for all standards Double data rate (DDR) 8-bit 4:2:2 YCrCb for all standards Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all standards
COMPOSITE AND S-VIDEO PROCESSING
* Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N, 60) and SECAM B/D/G/K/L standards in the form of CVBS and S-video Superadaptive 2D 5-line comb filters for NTSC and PAL give superior chrominance and luminance separation for composite video Full automatic detection and autoswitching of all worldwide standards (PAL/NTSC/SECAM) Automatic gain control with white peak mode ensures the video is always processed without loss of the video processing range Adaptive digital line length tracking (ADLLTTM)
*
* *
*
Rev. SpA | Page 13 of 20
ADV7401
COMPONENT VIDEO PROCESSING
* * Formats supported include 525i, 625i, 525p, 625p, 720p, 1080i, and many other HDTV formats Automatic adjustments include gain (contrast) and offset (brightness); manual adjustment controls are also supported Support for analog component YPrPb/RGB video formats with embedded sync or with separate HS, VS, or CS Any-to-any, 3 x 3 color space conversion matrix supports YCrCb-to-RGB and RGB-to-YCrCb Standard identification (STDI) enables system level component format detection Synchronization source polarity detector (SSPD) determines the source and polarity of the synchronization signals that accompany the input video Certified Macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) Free-run output mode provides stable timing when no video input is present Arbitrary pixel sampling support for nonstandard video sources * * *
DIGITAL VIDEO INPUT PORT
* * * Supports raw 8-bit CVBS data from digital tuner Support for 24-bit RGB input data from DVI Rx chip, output converted to YCrCb 4:2:2 Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, VGA to SXGA @ 60 Hz input data from HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
* * * *
GENERAL FEATURES
* * * * HS, VS, and FIELD output signals with programmable position, polarity, and width Programmable interrupt request output pin, INT, signals SDP/CP status changes Supports two I2C host port interfaces (control and VBI) Low power consumption: 1.8 V digital core, 3.3 V analog and digital I/O, low power power-down mode, and green PC mode Industrial temperature range (-40C to +85C) (except ADV7401KSTZ-140) 140 MHz speed grade (ADV7401KST-140) 100-lead, 14 mm x 14 mm, Pb-free LQFP
* * *
RGB GRAPHICS PROCESSING
* 140 MSPS conversion rate supports RGB input resolutions up to 1280 x 1024 @ 75 Hz (SXGA); (110 MSPS conversion rate for ADV7401BSTZ-110); (80 MSPS conversion rate for ADV7401BSTZ-80) Automatic or manual clamp and gain controls for graphics modes Contrast and brightness controls 32-phase DLL allows optimum pixel clock sampling Automatic detection of sync source and polarity by SSPD block Standard identification is enabled by STDI block RGB can be color space converted to YCrCb and decimated to a 4:2:2 format for video centric backend IC interfacing Data enable (DE) output signal supplied for direct connection to HDMI/DVI Tx IC Arbitrary pixel sampling support for nonstandard video sources
* * * * * *
* *
Rev. SpA | Page 14 of 20
ADV7401 DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7401 analog front end comprises four 10-bit ADCs that digitize the analog video signal before applying it to the SDP or CP (see Table 8 for sampling rates). The analog front end uses differential channels to each ADC to ensure high performance in a mixed-signal application. The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7401. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping in either the CP or SDP. Optional antialiasing filters are positioned in front of each ADC. These filters can be used to band-limit standard definition video signals, removing spurious, out-of-band noise. The ADCs are configured to run in 4x oversampling mode when decoding composite and S-video inputs; 2x oversampling is performed for component 525i, 625i, 525p, and 625p sources. All other video standards are 1x oversampled. Oversampling the video signals reduces the cost and complexity of external anti-aliasing filters with the benefit of an increased signal-tonoise ratio (SNR). The ADV7401 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed and output under control of I2C registers and the fast blank pin. Table 8. Maximum ADC Sampling Rates
Model ADV7401BSTZ-80 ADV7401BSTZ-110 ADV7401KSTZ-140 Maximum ADC Sampling Rate 80 MHz 110 MHz 140 MHz
The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to tuner SAW filter. The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. The ADV7401 implements a patented adaptive-digital-linelength-tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7401 to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The SDP also contains a chroma transient improvement (CTI) processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image. The SDP can process a variety of VBI data services, such as TeleText, closed captioning (CC), wide screen signaling (WSS), video programming system (VPS), vertical interval time codes (VITC), copy generation management system (CGMS), Gemstar 1x/2x, and extended data service (XDS). The ADV7401 SDP section has a Macrovision 7.1 detection circuit that allows it to detect Types I, II, and III protection levels. The decoder is also fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR
The CP section is capable of decoding/digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, VGA up to SXGA @ 75 Hz (ADV7401KSTZ-140 only), and many other standards not listed here. The CP section of the ADV7401 contains an AGC block. When no embedded sync is present, the video gain can be set manually. The AGC section is followed by a digital clamp circuit that ensures the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); manual adjustment controls are also supported. A fully programmable, any-to-any, 3 x 3 color space conversion matrix is placed between the analog front end and the CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color space converter.
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of baseband video signals in composite S-video and YUV formats. The video standards supported by the SDP include PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7401 can automatically detect the video standard and process it accordingly. The SDP has a 5-line superadaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required.
Rev. SpA | Page 15 of 20
ADV7401
The output section of the CP is highly flexible. It can be configured in single data rate mode (SDR) with one data packet per clock cycle or in a double data rate (DDR) mode where data is presented on the rising and falling edges of the clock. In SDR mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these modes HS, VS, and FIELD/DE (where applicable) timing reference signals are provided. In DDR mode, the ADV7401 can be configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb pixel output interface with corresponding timing signals. The ADV7401 is capable of supporting an external DVI/ HDMI receiver. The digital interface expects 24-bit 4:4:4 or 16-bit 4:2:2 bit data (either graphics RGB or component video YCrCb), accompanied by HS, VS, DE, and a fully synchronous clock signal. The data is processed in the CP and output as 16-bit 4:2:2 YCrCb data. The CP section contains circuitry to enable the detection of Macrovision encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. VBI extraction of CGMS data is performed by the CP section of the ADV7401 for interlaced, progressive, and high definition scanning rates. The data extracted can be read back over the I2C interface. For more detailed product information about the ADV7401, contact your local ADI sales office or email video.products@analog.com.
Rev. SpA | Page 16 of 20
ADV7401 PIXEL INPUT/OUTPUT FORMATTING
Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)
Processor, Format, and Mode 19 SDP Video out, 8-bit, 4:2:2 SDP Video out, 16-bit, 4:2:2 SDP Video out, 24-bit, 4:4:4 SM-SDP Digital tuner input[1] CP 8-bit, 4:2:2, DDR D7 CP 12-bit, 4:4:4, RGB D7 DDR CP Video out, 16-bit, 4:2:2 CP Video out, 24-bit, 4:4:4 SM-CP HDMI receiver support, 24-bit, 4:4:4 input SM-CP HDMI receiver support, 16-bit, pass-through 18 17 16 15 14 YCrCb[7:0]OUT Y[7:0]OUT Y[7:0]OUT 13 12 Pixel Port Pins P[19:0] 11 10 9 8 7 6 5 4 3 2 1 0 -
CrCb[7:0]OUT Cb[7:0]OUT
Output choices are the same as video out 16-bit or pseudo 8-bit DDR D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 R[5:4]IN D11 D10 D9 D8 -
CHA[7:0]OUT (for example, Y[7:0]) CHA[7:0]OUT (for example, G[7:0]) CHA[7:0]OUT (for example, Y[7:0])
CHB/C[7:0]OUT (for example, Cr/Cb[7:0]) CHB[7:0]OUT (for example, B[7:0]) CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
R[1:0]IN
CHA[7:0]OUT (for example, Y[7:0])
-
-
CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
-
-
Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)
Processor, Format, and Mode SDP Video out, 8-bit, 4:2:2 SDP Video out, 16-bit, 4:2:2 SDP Video out, 24-bit, 4:4:4 SM-SDP Digital tuner input[1] CP 8-bit, 4:2:2, DDR CP CP CP SM-CP 12-bit, 4:4:4, RGB DDR Video out, 16-bit, 4:2:2 Video out, 24-bit, 4:4:4 input HDMI receiver support, 24-bit, 4:4:4 input HDMI receiver support, 16-bit, pass-through 40 39 38 37 36 35 Pixel Port Pins P[40:31], P[29:20] 34 33 32 31 29 28 27 26 25 24 23 22 21 20 -
Cr[7:0]OUT -
DCVBS[7:0]IN -
CHC[7:0]OUT (for example, R[7:0]) B[7:0]IN
G[7:0]IN
R[7:6]IN
R[3:2]IN
SM-CP
CHA[7:0]IN
-
-
CHB/C[7:0]IN
-
-
Rev. SpA | Page 17 of 20
ADV7401 RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
The external loop filter components for the ELPF pin should be placed as close as possible to the respective pins. Figure 8 shows the recommended component values.
PIN 46-ELPF 1.69k 10nF
82nF PVDD = 1.8V
05340-007
Figure 8. ELPF Components
Rev. SpA | Page 18 of 20
AVDD_3.3V DVDDIO DVDD_1.8V U1 BYPASS CAPACITORS U1 BYPASS CAPACITORS
U1 BYPASS CAPACITORS
PVDD_1.8V
0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 10nF 10nF 10nF 10nF 10nF
10nF 10nF
AGND
75 75 75 75 75 75 75 75 56
DVDDIO DVDD_1.8V PVDD_1.8V AVDD_3.3V C94 1nF U1
AGND
AGND DGND
DGND
P5-2
0.1F
47 PVDD PVDD 48 AVDD 63 DVDD 12 DVDD 39 90 DVDD
GREEN
P5-3
0.1F 0.1F
52 54 56 58 SOG AIN1 AIN2 AIN3
BLUE
75
VP[00:41]
P5-1
RED
TYPICAL CONNECTION DIAGRAM
P5-14
VS_IN
AGND
C22 1nF
72 74 76 77 AIN4 AIN5 AIN6 SOY
P6-5 P6-6 P5-7 P5-8 P5-10
Pr/Pb Pb/Pr Y AGND
10F 0.1F 0.1F 10nF
PHONO3 0.1F 0.1F 0.1F
53 AIN7 55 AIN8 57 AIN9 69 CAPC2 68 CAPC1 62 CAPY2 61 CAPY1
6 DVDDIO 18 DVDDIO
RGB GRAPHICS
P5-13
HS_IN
DE_IN P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 INT DCLK_IN
79 83 84 87 88 95 96 97 100 1 2 3 35
1 2 3 4 5 6
71 AIN10 73 AIN11 75 AIN12
33 33 33 33 33 33 33 33 33 33 33 33
VP41 VP40 VP39 VP38 VP37 VP36 VP35 VP34 VP33 VP32 VP31 VP30
INT DCLCK_IN
P7
P4 SCART_21_PIN 0.1F
AGND 0.1F AGND 10F 0.1F 10nF
+ 10F
ADV7401
21 0.1F
0.1F
AGND
20 CVBS/Y Y2
28.63636MHz
19 PVDD_1.8V 82nF 1M 47pF1 5.6k DGND SDA SCLK RESET Y C 100 100 10nF 47pF1 1.69k
2.7k
70 TEST0 66 AVSS 60 AVSS
49 PVSS 50 PVSS
5 DVSSIO 17 DVSSIO
11 DVSS 40 DVSS 89 DVSS
Rev. SpA | Page 19 of 20
2.7k
Figure 9. ADV7401
0.1F
0.1F
+ 10F
16 2 11 15
F_BLNK BLUE GREEN RED/C
65 CML 64 REFOUT 67 BIAS
P29 P28 P27 P26 P25 P24 P23 P22 P21 P20
13 14 24 29 30 31 32 33 34 45
33 33 33 33 33 33 33 33 33 33
VP29 VP28 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20
38 XTAL 37 XTAL1 46 ELPF 81 SDA 82 SCLK 19 SDA2 16 SCLK2 80 ALSB 78 RESET
20 18 16 14 12 10 8 6 4 2 19 0.1F 0.1F DVDDIO AGND
19 17 15 13 11 9 7 5 3 1
S-VIDEO
3
4
P8
1
2
1 2 3 4
P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 LLC1 51 FB
91 92 93 94 7 8 9 10 20 21 22 23 25 26 27 28 41 42 43 44 36
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 100 100 100 100 100 100 59 D1 BZX399-C3V3 TEST1 SFL/SYNC_OUT 15 33
VP19 VP18 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP09 VP08 VP07 VP06 VP05 VP04 VP03 VP02 VP01 VP00 LLC1
MINI-DIN-4
CVBS 19 P9
0.1F
HS 4 VS 99 FIELD 98 HREF/HS_IN 86 VREF/VS_IN 85
HS VS FIELD HS_IN VS_IN SFL/SYNC_OUT
56
AGND
DVDDIO BAT54C K2
AGND DGND
K1
1LOAD
CAP VALUES ARE DEPENDANT ON CRYSTAL ATTRIBUTES
10k
05340-009
ADV7401
ADV7401 OUTLINE DIMENSIONS
1.60 MAX 0.75 0.60 0.45
100 1 PIN 1
16.20 16.00 SQ 15.80
76 75
TOP VIEW
(PINS DOWN)
14.20 14.00 SQ 13.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 COPLANARITY
25 26
51 50
VIEW A
0.50 BSC LEAD PITCH
VIEW A
ROTATED 90 CCW
0.27 0.22 0.17
051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADV7401BSTZ-802 ADV7401BSTZ-1102 ADV7401KSTZ-1402 EVAL-ADV7401EBM
1
Temperature Range -40C to +85C -40C to +85C 0C to 70C
Package Description 100-Lead Low Profile Quad Flat Package (LQFP) 100-Lead Low Profile Quad Flat Package (LQFP) 100-Lead Low Profile Quad Flat Package (LQFP) Evaluation Board
Package Option ST-100 ST-100 ST-100
The ADV7401 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255C (5C). In addition, it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220C to 235C. 2 Z = Pb-free part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05340-0-9/05(SpA)
Rev. SpA | Page 20 of 20

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